VDMOS transistors of various voltage and current ratings are these days the device of choice for high-frequency switching power supplies as they are incorporated in a wide variety of power control and conversion applications for space and military systems. Outer space applications such as communication satellites, weather satellites, GPS (Global Positioning Systems) and earth observations use many Power MOSFETs due to their high switching speed, low conduction losses and small foot print. One extra requirement for MOS (Metal Oxide Semiconductor) devices operating in outer space is long term reliability, with high tolerance to ionizing radiation, high energy particles and the like. For VDMOS Power Transistors, threshold voltage (Vth), blocking voltage (BVdss), leakage current (Idss), transconductance (Gm) and On Resistance (Rdson) are all affected by the ionizing radiation and therefore a Power MOSFET suitable for such an application has to be “radiation hardened” by design and fabrication process.
From the very beginning of using VDMOS devices in space applications, Single Event Burnout (SEB) was immediately identified as one of the main limitations of using commercial VDMOS devices in environments with increased flux of heavy ions. Much research has been devoted to SEB and to means to improve the capability of a VDMOS device under the bombardment of heavy ions. In summary, a high energy ion creates a “sheath” of electric charge along its path inside the semiconductor, proportional with its LET (Linear Energy Transfer).
If the drain bias of the VDMOS device exceeds certain values (or the electric field in the device approaches critical values) then, locally and within diameters smaller than one micron, the hole-electron density is increased, inducing current densities in excess of 104 A/cm2. Holes will be driven toward the surface for an N-Channel MOSFET and underneath the source layer of the VDMOS device and can easily develop a voltage drop close to or higher than 0.7V, turning on the parasitic bipolar transistor inherent to any VDMOS structure.
The doping of the P-Well underneath the source, the length of the source and the length of the channel are the main design and process parameters one has to optimize and control in order to increase the survivability of VDMOS transistor to heavy ions. Therefore, the placement of the heavy doping underneath the source or the alignment of the source inside of the P-Wells are of the utmost importance as slight lateral variations in the placement of these heavily doped layers can create uneven turn-on (sooner than desired) of the parasitic NPN transistor and lead to destruction of the Power MOSFET.
When the parasitic bipolar transistor gets turned on, it enters in what is called secondary breakdown of the NPN (for a N-Channel VDMOS), or the “snap back” mode of operation. Once the secondary breakdown phenomenon has been triggered, the entire energy of the power supply gets “dumped” at the location on the die where this mode of operation has been initiated. Following that, the local temperature of the die increases tremendously and the junctions of the device become shorted due to diffusion of the top metals into semiconductor.
The most common way to reduce the propensity of the parasitic NPN to turn on is to increase the doping of the P-Well underneath the source. Increasing the doping of what is called the UIS (Unclamped Inductive Switching) implant layer has its own limitations as the doping of this layer can easily reach the silicon-silicon dioxide interface (channel region) and, when it does that, the threshold voltage of the part, at that location, has a sharp increase, virtually making a “dead” MOSFET at that location. The diffusion of the UIS layer into the channel is exacerbated if the location of the implant is improperly placed, in other words, if one side of the implant is closer to the channel region. Therefore, as important as the doping level, perfect placement (or perfect “alignment”) of the UIS layer in relationship to the source or the P-Well is the goal of any manufacturer of radhard MOSFETs.
As is known in the art, the gate of a lateral semiconductor device can be “self-aligned” to its corresponding source and drain regions. In such cases, the gate is used to mask a dopant implantation step that is performed to create the source and drain regions. Dopant is implanted in regions not blocked by the gate, and dopant is not implanted in regions blocked by the gate. As a result, an edge of the source region and an edge of the drain region are tightly aligned with edges of the gate, and subsequent drive or diffusion steps will ensure that the gate overlaps the edge of the source and drain regions. Therefore, in lateral devices, by ensuring the critical characteristic of the gate's overlap of the source and drain regions, this gate “self-alignment” technique may result in improved device performance.
In vertical DMOS semiconductor device fabrication, self-alignment of the source and body diffusions is itself important to providing symmetrical channel lengths and uniform channel structures. Both lateral MOS and vertical DMOS self-aligned processes rely on early formation of the gate structure, to which the body and source diffusions are self-aligned. As described in U.S. Pat. No. 4,259,779, however, forming a gate oxide after relatively high-temperature fabrication steps (such as those used to create doped regions in a substrate) may prevent substantial degradation of the radiation resistance of vertical DMOS semiconductor devices. This procedure, referred to as late-gate formation, is inconsistent with the foregoing self-alignment procedures.
Recent research, simulation and experimental work have demonstrated that increasing the secondary breakdown of the parasitic NPN transistor can be achieved if the electric field at the transition region between the epitaxial (“epi”) layer and the substrate is “tailored” by using two epi layers (Liu, Sandra, “Effect of Buffer Layer on Single Event Burnout of Power DMOSFETs”, IEEE 2007, NSREC Paper No PJ-5 and Liu, Sandra, “Single-Event Burnout and Avalanche Characteristics of Power DMOSFETs,” IEEE 2006, NSREC Paper No. 6, Vol. 53, December 2006). By increasing the doping of the first epi layer (the one closer to the substrate), the carrier multiplication in the presence of high electric field and in the presence of charge generated by the heavy ion is minimized (“avalanche injection” effect is minimized, see Beatty, Brent A, “Second Breakdown in Power Transistor due to Avalanche Injection, IEEE Transactions on Electron Devices, Vol. ED-23, No. 8, August 1976). By creating a lower electric field “charge multiplication effect” is also lower and therefore less carriers are driven toward the ground terminal, with lower chances that the NPN parasitic bipolar will be turned on.
As shown by the work of Sandra Liu, the addition of a buffer epitaxial layer is an improvement but the “snap back” phenomenon is still present, nevertheless at higher voltages, but it is still there. This approach has the drawback that any additional epitaxial layers, regardless of their doping, are detrimental to the Rdson of the VDMOS and therefore a tradeoff between the secondary breakdown and the On Characteristics of the device has to be accepted.
Accordingly, a need remains for a better way to make radiation resistant (“radhard”) power MOSFET devices.